1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.
2. Description of the Related Art
In recent years, magnetoresistive memories have been developed (for example, see Japanese Unexamined Patent Application Publication No. 2013-93592 (hereinafter referred to as '592 document)).
According to a known structure of a STT-MRAM array such as one shown in FIG. 4A of '592 document, source lines (SL) extend perpendicular to word lines (WL) and parallel to bit lines (BL). When this structure is formed by using planar transistors, an additional metal 1 is needed for source lines as shown in FIG. 4B of '592 document and thus the area used in the bit cell array is increased and the size of the bit cell is increased.
There have been proposals of surrounding gate transistors (hereinafter referred to as SGTs) in which a source, a gate, and a drain are arranged in a direction perpendicular to a substrate and in which a gate electrode surround a pillar-shaped semiconductor layer (for example, see Japanese Unexamined Patent Application Publication No. 2004-356314).
However, since the density of silicon is 5×1022 atoms/cm3, it becomes increasingly difficult to introduce an impurity into a silicon pillar as the silicon pillar becomes thinner.
A proposal has been made for existing SGTs that the threshold voltage of a SGT be determined by decreasing the impurity concentration of channel to 1017 cm3 or less and changing the work function of the gate material (for example, see Japanese Unexamined Patent Application Publication No. 2004-356314).
Another proposal relates to a planar MOS transistor, in which a side wall in a LDD region is formed of polycrystalline silicon having the same conductivity type as the low-concentration layer and surface carriers in LDD region are induced by the difference in work function. As a result, compared to a LDD-type MOS transistor having a side wall formed of an oxide film, the impedance in the LDD region can be decreased (for example, see Japanese Unexamined Patent Application Publication No. 11-297984). According to this document, the polycrystalline silicon side wall is electrically insulated from the gate electrode and figures show that the polycrystalline silicon side wall and the source/drain are insulated from each other by an interlayer insulating film.